GitHub

apoorvvuppulury7/Asynchronous-FIFO-Buffer

Gray code counters are used in FIFO design because they only allow one bit to change for each clock transition. This characteristic eliminates the problem associated with trying to synchronize ...
TechRepublic

Verification of Asynchronous FIFO Using System Verilog

FIFO (First In First Out) is a buffer that stores data in a way that data stored first comes out of the buffer first. Asynchronous FIFO is most widely used in the System-on-Chip (SoC) designs for data ...
IEEE

128-bit Asynchronous Gray Code FIFO using Verilog HDL

Abstract: This paper presents the design and implementation of a 128-bit Asynchronous Gray Code FIFO using Verilog HDL. The FIFO is designed for bidirectional transfer of data between different clock ...
EDN

Understanding Asynchronous FIFOs

This application note explains the internal architecture of the asynchronous FIFO made by Cypress (CY7C421) and its functionality – the writing and reading process. It also discusses FIFO ...
IEEE

Asynchronous FIFO Design Based on Clock Gating Power Optimization

Abstract: Asynchronous First in First Out (FIFO) is critical for data buffering and clock domain crossing in modern digital systems, but their power consumption and reliability under metastability ...