EDN

SoC design: When a network-on-chip meets cache coherency

Many people have heard the term cache coherency without fully understanding the considerations in the context of system-on-chip (SoC) devices, especially those using a network-on-chip (NoC). To ...
Design-Reuse

New 64-Bit RISC Microprocessor from Toshiba Utilizes 0.13-Micron Process Technology to Achieve 300MHz Operating Frequency

SAN JOSE , Calif., October 29, 2002 -- Toshiba America Electronic Components, Inc. (TAEC) today announced a new addition to its TX49 family of MIPS-based reduced instruction set computer (RISC) ...
Electronic Design

Adding Cache to IPs and SoCs

Cache memory significantly reduces time and power consumption for memory access in systems-on-chip. Technologies like AMBA protocols facilitate cache coherence and efficient data management across CPU ...
mccormick.northwestern.edu

Microprocessor System Design Students Demo Final Projects

Integrating processors, sensors, and data exchange functionality into everyday objects, the Internet of Things (IoT) pushes computing capabilities far beyond desktops and servers. On December 5, ...
Design-Reuse

Toshiba launches new 64-Bit RISC microprocessor, its first standard processor based on high-performance TX99/H4 core and industry-leading 90nm process technology

SAN JOSE, Calif., July 6, 2004 - Toshiba America Electronic Components, Inc. (TAEC)* today announced the introduction of a new 64-bit single-chip MIPS-basedâ„¢ reduced instruction set computer (RISC) ...