GitHub

Behavioral Modelling of Phase-Locked Loop using Deep Learning Techniques

Phase-locked loops (PLLs) are the heart of many electronic systems. PLL designs can be large and complex. They have a unique property that makes their analysis and simulation even just for their ...
IEEE

Design and Performance Analysis of Phase Lock Loop using ANFIS under Non-Ideal Conditions

Abstract: The following paper briefs about design and performance analysis of phase lock loop (PLL) of an inverter under non ideal grid conditions using adaptive network based fuzzy inference system ...
EDN

Phase-Locked Loop Applications

This application note discusses phase frequency detector characteristics that affect phase-locked loop (PLL) dead band and jitter performance. In PLLs that employ charge pump loop filter designs the ...
IEEE

Multi-phase bang-bang digital phase lock loop with accelerated frequency acquisition

Abstract: A highly digital phase lock loop with a multi-phase bang-bang phase detector is proposed to speed up lock time and to increase the pull in range. To reduce power consumption, the high speed ...
Electronic Design

Phase-Noise Modeling, Simulation, and Propagation in Phase-Locked Loops (Part 3)

Some brief theory and typical measurements of phase noise. How to produce the lowest phase noise at a PLL output. A standard design procedure for a typical Type 2, second-order loop. As stated in ...